System for the modification of data stored in recirculating delay lines

ABSTRACT

In a telecommunication system of the time-sharing type wherein several calls are concurrently conducted over a common line circuit by means of interleaved message signals recurring in a predetermined order, command pulses relating to the several calls are sequentially directed to the input of a register with several parallel memory stages each including a delay line whose delay time encompasses a number of pulse cycles equal to the maximum number of calls to be accommodated simultaneously by the line circuit. Digital pulses traveling along each memory stage are continuously fed back from the output to the input thereof for reinscription until modified by a command signal applied to all the memory stages through a logic matrix for carrying out such operations as &#39;&#39;&#39;&#39;enter 1,&#39;&#39;&#39;&#39; &#39;&#39;&#39;&#39;enter 0,&#39;&#39;&#39;&#39; &#39;&#39;&#39;&#39;inscribe new number,&#39;&#39;&#39;&#39; &#39;&#39;&#39;&#39;add 1&#39;&#39;&#39;&#39; and &#39;&#39;&#39;&#39;subtract 1.

United States Patent [72] Inventors Giorgio 3,405,392 10/1968 Milne et a1 340/1725 Saverro Martmelh; Aldo Perna, all of 3,471,835 10/1969 Gribble et al. 235/165 X My OTHE EFERENCES [21] Appl. No. 735,606 R R J. E. Elliott; lncrement-Decrement Logic IBM Technical [22] Filed June 10, 1968 B n V l l N 3 A 968 97 [45] Patented septum 1971 29issclosure u etin, o 1 o. ugust, l PP- 2 [731 Assignee Societa Italians Telecomunicazioni Siemens S.p.A. Primary Examiner-Malcolm A. Morrison Milan, Italy Assistant Examiner-David H. Malzahan [32] Priority June 9, 1967 Attorney-Karl F. Ross [33] Italy 17,009/68 ABSTRACT: In a telecommunication system of the time-shar- 5 SYSTEM FOR THE MODIFICATION DATA ing type wherein several calls are concurrently conducted STOREDIN RECIIICULATING DELAY LINES over a common line circuit by means of interleaved message 11 Cl i 5 Drawing Figs signals recurring in a predetermined order, command pulses 4 relating to the several calls are sequentially directed to the U.S. -v in ut of a regi ter several parallel memory stages each in- 235/167 eluding a delay line whose delay time encompasses a number [51] Int. CL 606i 7/50 f puIse cycles equal to the maximum number f calls to be [50] Field of Search 235/168, commodated simultaneously by the line circuit Digital pulses 92 traveling along each memory stage are continuously fed back from the output to the input thereof for reinscription until [56] References Cited modified by a command signal applied to all the memory UNITED STATES PATENTS stages through a logic matrix for carrying out such operations 3,414,889 12/1968 Higgins et al. 340/173 as "enter 1, enter 0, inscribe new number, add 1" and 3,370,158 2/1968 Lehmer 235/168 X subtract 1,"

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L A l 3.603774 saw an? 4 omenemmnou D cuzcun- FLIP-V FLOP ATI'ORN EY SYSTEM FOR THE MODIFICATION OF DATA STORED IN RECIRCULATING DELAY LINES Our present invention relates to a counting register for concurrently storing numerical information relating to a plurality of. different items, such as telephone calls and other message transmissions in telecommunication systems, and for. modifyingthe information so stored.

Theuse of electronic circuitry in computing the charges for telecommunication services, while highly advantageous, has not yet become universal. Difficulties exist, for example, in the case of: telephone systems wherein. several conversations are carried on simultaneously over a common. trunk line, by the time-sharing technique, with the aid of interleaved code signals representing the instantaneous amplitudes of voicefrequency currents to be transmitted. It is known to compute the charge for each individual call on the basisof counting pulses periodically transmitted at a frequency depending upon the distance between the two interconnected subscribers; while the counting pulses pertaining .to several concurrent message transmissions may be interleaved in the same predetermined order as the corresponding message signals, the routing of these pulses to differentcounting registers requires an involved circuit arrangement. The system becomes even more complex. when different classes of calls are to be handled simultaneously by the same line circuit, such as local calls subjectto a unit charge, toll calls charged to the account of the calling subscriber, and prepaid calls (e.g. from coin-operated stations) with progressive depletion. of a preestablished credit balance.

An object of our invention is to provide a single register adapted to be used for the simultaneous storage of different trains of counting pulses, arriving in a predetermined cyclic succession, for individually computing the cost of several simultaneous telephone conversations or other overlapping eventssubject to different rates. of charge.

Another object is to provide a universal register capable. of utilization with a variety of different classes of service, such as. those mentioned above, some of which may involve a recording of fixed numerical values while others may require an additive or subtractive modification of a value previously registered.

Thus, in a comprehensive charge-calculating system of the. type specifically contemplated herein, the register should beresponsive to command signals of the: following character:

a. unit signals applying to local calls;

b. recurrent counting pulsesrelating to toll calls;

c. numerical pulses for entering a credit balance (e.g. upon the deposition of one or more coins) from which a unit issubtracted in response to each calling pulse;

d. cancellation signalsto clear the. register.

A more particular object of our invention is therefore to. provide a register capable of storing a number of .words" for an indefinite period, and of modifying a selected word in response to any one ofthe aforementioned command signals upon the occurrence of such command signal at a particular point of an operating cycle.

in accordance with our invention, a register for the concurrent storage and selective modification of a plurality of binary words, conveying the numerical information referred to, com prises several substantially identical parallel memory stages, each stage, including a delay line for the transmission of a series of digitalpulses from an input of each stage to an output thereof; the fundamental recurrence period 1' of. these digital pulses is an aliquot part of the delay time t of each of these, lines, i.e. of an. operating cycle of the register, so that t=pr wherein p is the maximum number of digital pulses that can be accommodated at any time on the delay line of any one stage; Thus, p also represents the number of telephone calls or other messages concurrently transmittable over a line circuit associated with such register.

ln orderto perpetuate the information stored on. the register, in theabsence ofa cancellationtor modification signal, the output endof eachdelay line is coupled; tothe input end thereof through a feedback circuit which periodically reinscribes every digital pulse propagating along the line until a command .pulse is applied to a logic matrix, includedv in the feedback path. This logic matrix is dividedinto as many secleads for producing a control pulse which energizes the as? sociated delay line to generate a digital pulse traveling therealong. In a preferred embodiment, these, logic gates in clude several AND gates per section and a common OR gate 7 according to our invention. is the algebraic summing, i.e. the

performance of additionsor subtractions,; in response. toa command such as .ADD.1"' or SUBTRACT I delivered to the logic matrix. Depending upon the value of' the stored I number which is to be subjected to such incremental modifn' cation, one or more bits of a circulatingword must be changed into. their complements so that every register stage is poten-. tially affected. In the first section of the logic matrix, assigned to the stage for the lowesvorder digit, a l must be inscribed in lieu of a previous O," and vice versa, forboth addition .and-

subtraction; thiscan be accomplished with the aid of an AND gate connected, on the one hand, to a command lead carrying the adding pulse C or the subtracting pulse C, and, on the other hand, to a feedback lead carrying a complementary output pulse U, representing the inverted value of a bit registered is the logical product of true values of the. binary outputs of all Y the preceding stages (h being any integer smaller than k),Z,,. is the complement of Z,,.,

Yk E II T71.

is the analogous product of the inverted values, and Y is the complement of Y, Since the complement of a logical. product,

equals the logical sum of the complements, we'can also write plicity an EXCLUSIVE-OR gate connected to receive the input signals Z or Y and U In the second section, this EX- CLUSIVEOR gate is thus connected to two leads respectively carrying. for adding, the signals U,, U, and, for subtracting, the signals 13,, U,; in the third and subsequent stages, the EX- CLUSIVE-OR gate is preceded by an AND gate which forms the product 2,, or Y from the direct or the complementary output pulses U,, U: or U U, etc. of the lower-order stages.

Each matrix section may also include further AND gates responsive to other command pulses, such as an entry signal coupled with a numerical pulse to register a bit of a new number, or a unit pulse to register a 1" in a particular stage (usually the first stage), and to the absence of any command pulse to reinscribe a stored bit in the same stage.

According to another feature of our invention, each memory stage includes an input flip-flop and an output flipflop, the former being settable by the coincidence of a control signal S with a first clock pulse and being resettable by a second clock pulse to generate a digital pulse of a duration shorter than the recurrence period T; this digital pulse, on reaching the other end of the delay line, is differentiated so as to produce a spike (preferably coinciding with its leading edge) for tripping the output flip-flop which is then reset by a third clock pulse. The first, second and third clock pulses are periodically generated with identical cadences equal to 1/1, i.e to the reciprocal of the recurrence period.

The above and other features of our invention will become more clearly apparent from the following detailed description of a representative embodiment, reference being made to the accompanying drawing in which:

FIG. 1 is an overall block diagram of a counting register according to the invention;

FIGS. 2 and 3 show different sections ofa logic matrix forming part of the register of FIG. 1;

FIG. 4 is a circuit diagram of a memory stage forming part ofthe register; and

FIG. 5 is a set of graphs used in explaining the operation of the system of FIGS. 14.

The counting register illustrated in FIG. 1 has input connections to a line circuit and output connections to a recorder, not further illustrated, as conventionally used in telecommunication systems to make a temporary or permanent record of charges accruing during a call. The register has a set of nine input leads terminating at a logic matrix RL, these leads being shown provided with individual switches SW representative of any mechanical or electronic circuit-closing means. The switches SW enable the selective energization of lead 1 by an ADD 1" command pulse C lead 2 by a SUBTRACT 1" command pulse C lead 3 by an entry command pulse T,., lead 4 by an INSCRIBE I" or unit command pulse T,, lead 5 by an INSCRIBE or cancellation command pulse T and leads 6, 7, 8 and 9 by respective numerical pulses E,, E E and E, representing the bits of a new binary number to be entered. Leads 1-5 include respective amplifier-inverters AI,, Al Al AI and AI the first four of these amplifier-inverters being provided with additional output leads 1', 2', 3 and 4' which carry the complements if t T, and T, of signals C C,, T, and 'I',, respectively; amplifier-inverter A1 generates only the complement T in its output.

Logic matrix RL has four output leads ll, 12, 13 and 14 delivering respective control signals 5,, S S and S to associated delay lines L,, L L and L Each delay line has two output leads 21, 21'; 22, 22'; and 24, 24; on these output leads there appear respective pulse pairs U,, U,; U U U U and U,, U The pulses U,-U hereinafter referred to as direct output pulses, represent the true values of bits inscribed in the respective delay lines whereas the pulses EH11. hereinafter referred to as complementary output pulses, represent the inverted values ofthese bits.

The energization of one or more leads 11-14 by a pulse S r-Si. or by two or more of such pulses occurring simultaneously, represeiits a word which is propagated along delay lines L,- L, under the control of several trains of clock pulses CK,, CK, CK, applied by a pulse generator, not furhter illustrated, to three leads 41, 42,43 multipled to all the memory stages.

A set of feedback loops 31, 31', 32, 32',"'33, 33', 34 and 34' extend from the output leads 21, 21' etc. to the input side of the logic matrix RL for the purpose of reinscribing the bits U,, U, etc. or of controlling the incremental modification of the registered words in the presence of a command pulse on lead 1 or 2. As illustrated in FIGS. 2 and 3, matrix RL comprises an orthogonal array of conductors including extensions of leads 1, I etc. and 31, 31' etc., these two sets of leads intersecting with other conductors terminating at four groups of logic gates defining four matrix sections respectively associated with the output leads 11, 12, 13 and 14. The first two sections, generating the control pulses S, and 8;, are illustrated in FIG. 2; the other two sections, producing the control pulses S and 5,, are shown in FIG. 3.

The matrix section associated with lead 11 serves to enter, modify, reinscribe or cancel the lowest-order bit of a 4-bit word, the other three sections serving the same functions for successively higher denominations. Naturally, the number of matrix sections (and of associated memory stages L,L.,) may be further increased if desired.

The lmatrix section is provided with five AND gates A,, A,, A A and A whose outputs are all multiplied to conductor 11 through a common OR gate 0,. The second sections contains four AND gates A A A,, and A,,, working into a common OR gate 0 and a pair of EXCLUSIVE-OR gates OE,, CE, in the inputs of gates A and A,, respectively. The third section has an OR gate 0, fed by AND gates A,,, A A and A two EXCLUSIVE-OR gates OE;, and 0B,, in the inputs of gates A, and A and two further AND gates A,,, and A,, ahead of gates 0E and OE respectively. The fourth section is of essentially the same construction as the third section, with four main AND gates A,,, A A,,, and A a common OR gate 0,, two EXCLUSIVE-OR gates 0E 0H,, and two auxiliary AND gates A,,, and A,,. Any higher-order matrix section would be analogous to the two sections illustrated in FIG. 3.

Each of the principal AND gates A, A A A and A,,, A has an input connected to leadS, which is energized in the absence of a cancellation signal INSCRIBE 0," thus carrying the command T Lead 4', carrying the command T,, is connected to the inputs of all the principal AND gates except those of the first section; its companion lead 4 feeds the complementary command T, to gate A, only. Lead 3, energized in response to the command T,,, is connected to gates A A A,, and A which also have inputs tied to leads 6, 7, 8 and 9, respectively; all the other principal AND gates have inputs connected to the companion lead 3' carrying the complementary command T,,. Lead 1 (command C is connected to gates A,, A,,, A and A,,, whereas lead 2 (command C,) supplies the gates A A A and'A their companion leads 1' (command G and 2 (command (3,) are tied to gates A A A,,, and A In addition, lead 31 (output U,) is connected to gates A OE, and A,,; lead 31' (output 0,) is tied to gates A,, A 05 A,, and A,,. Lead 32 (output U supplies the gates OE,, 0E A,,, A,,, and A,,,; lead 32 (output U feeds the gates A,, and A,,. Lead 33 (output U is tied to gates 0E 015,, A,,, and A,,; lead 33' (output U is connected to gate A,,. Lead 34 (output U energizes the gates 0E OE,, and A lead 34' (output U does not control any gates in the four-stage register illustrated in the drawing but would be needed if additional stages were used.

With the connections described above, the four control pulses appearing on leads 11-14 satisfy the following logical equations: I

51 U,c,,T,+ (7,031+ E.T.+ T. theorem (1) Using the symbols previously adopted, we may rewrite the first two terms of equations (2) in the form U 2, FU,Z,)C,T,+ U,Y,+U,Y, T, which, with conventional notation. can also be expressed as the circle sum 2$ 2) a e 2$ 2) x e;

by the same token, the corresponding terms of equations (3) i and (4) become U39 Y3 I e and Thus we can generalize these terms for any matrix section other than the first one in the form wtezn fiw W en- 01 E (112% Uta-min (U Y g -Uk U s E- More particularly, gates OIL-OE serve to form the circle sums of equations (2), (3) and (4) whereas the auxiliary AND gates A A and A A generate the logical products The logic matrix RL shown in FIGS. 1-3 functions iri the following manner: I

As long as all the switches SW are open, gates A A A and A2, are opened whenever a pulse U U U or U, appears on lead 31, 32, 33 or 34, respectively, so as to give rise to a corresponding command pulse S S S or S, which reinscribes the same output pulse on the associated delay line L,,

. L L or L Any word registered in these delay lines is thus continuously recirculated.

If a new word is to be entered, lead 3 must be energized I together with a selected combination of leads 6-9. If none of t the four bottom switches SW is closed whilethe entry command T is given on lead 3, this command acts as a cancellation signal (equivalent to energization of lead 5) by blocking Y the reinscription gates A A A and A If any of leads 6-9 is connected to potential at the same time, the corresponding gate A A A or A operates to enter a binary pulse or bit on the associated output lead 1 1, 12, 13 or 14.

Energization of lead 4 also inhibits reinscription but opens the gate A, to enter a bit in the units memory stage L Naturally, similar connections could be made to one or more of the otherstages if a numerical value other than 1 were to be registered upon closure of the No. 3 switch SW.

It is assumed that the two uppermost switches SW cannot be closed simultaneously so that energization of leads 1 and 2 is .mutually exclusive, hence no interdictory cross-connection ,need to be made between leads 1', 2' and the gates connected to leads 2 and 1, respectively. It will be readily apparent that,

with the circuitry shown and described, energization of lead 1 ,adds the value of unity to an amount stored in the memory L -L whereas energization of lead 2 subtracts this amount from the stored value. During such addition or subtraction, recirculation through gates A A A and A is, of course, inhibited.

Reference will now be made to FIG. 4 for a description of a memory stage L representative of any of the four stages L,L

:shown in FIG. 1.

Memory stage L, has four input leads 10, 41, 42 and 43,

. lead 10 being representative of any one of leads 11-14 in FIG.

Tw wound around one end ofa magnetostrictive wire F whose other end similarly traverses a reading coil Tr in the input ofa reading amplifier Ar; a permanent or electrically excited magnet M generates a biasing field axially along coil Tr. The delayed signal picked up by coil Tr is amplified and rectified in amplifier Ar and differentiated in a circuit D which has an output connected to the setting input Sr of a reading flip-flop or bistable multivibrator Br; the resetting input Rr of this flipflop is tied to lead 43. Flip-flop Br has two outputs 30 and 30' (representative of any of leads 31-34 and 31 '-34') which are alternately energized to generate the output signal U or-U,

The operation of the memory stage L, will now be described with reference to FIG. 5.

Graph (a) of FIG. 5 shows the control pulse 8,, which has a width somewhat greater than that of clock pulses CI(,, CK CK illustrated in graphs (b), (e) and (d), respectively. Gate Ew, opened during the period of overlap of pulses S and CK,, generates on input pulse I graph (0), which trips the flip-flop Bw to initiate the generation of a binary pulse P graph (1), transmitted along delay line F. After a delay of duration t=pr (7 being the recurrence period of clock pulses CI(,, CK and CK,,,), this binary pulse is picked up by coil Tr as a pulse P shown in graph (g). The latter pulse is then differentiated to deliver a spike 0,,- coinciding with its leading edge, the corresponding trailing-edge spike of opposite polarity being suppressed by a rectifier not shown. Spike Q, in tripping the flipflop Br, starts an output pulse U which is terminated by the occurrence of the next clock pulse CK so that its width is independent of that of pulse P which may have undergone some deformation in its travel along line F.

Thus, the width of pulse P is determined by the relative staggering of pulse trains CK, and CK whereas, if p is a whole number, the width of pulse U substantiallyequals the phase difference between pulse trains CK, and CK If control pulse 5,, is a replica of a previous output pulse U, to be reinscribed, the two pulses will of course have the same width.

The maximum number of pulses P propagating simultaneously along wire F is equal to p=t/'r. Naturally, the command pulse in the input of matrix RL (FIG. 1) must be timed to coincide, substantially, with a single clock pulse CK,-and, like pulses S and U,,., must have a width smaller than the recurrence period 1. If the register is used in a telephone system for the concurrent transmission of calls over a common line circuit by the time-sharing method described above, eg as disclosed in commonly owned application Ser. No. 636,164 filed 4 May 1967 by Fabio Balugani et al., the period 1- should of course correspond to the duration of a coding interval allotted to the sampling of a message signal, such interval being usually on the order of microseconds.

We claim:

1. A counting register for concurrently storing a plurality of binary words conveying numerical information relatingto a plurality of different items and for selectively modifying the information so stored, comprising:

a plurality of substantially identical parallel memory stages including each a delay line for the transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said delay line being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said delay line;

a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective delay line thereof;

feedback means connecting the output of each stage with the input thereof through said logic matrix for periodically reinscribing each digital pulse on the same delay line to perpetuate the information stored in said register stages;

and command means connected to said logic matrix for modifying, during a selected recurrence period, the information to be reinscribed;

said logic matrix comprising a first section for the lowestorder memory stage and an additional section for each higher-order memory stage, a first set of leads common to all said sections and selectively energizable by said command means, a second set of leads common to all said sections and selectively energizable by said feedback means, and a plurality of logic gates in each section having input connections to respective combinations ofleads from said first and second sets and having a single output connection to the input of the corresponding memory stage.

2. A counting register as defined in claim 1 wherein each of said stages is provided with an input flip-flop and an output flip-flop, a source of first and second clock pulses connected to said input flip-flop for respectively setting and resetting same in the presence of a control pulse in the output of said logic matrix, the input flip-flop being connected to energize said delay line in response to said first and second clock pulses for generating therein a digital pulse of a duration shorter than said recurrence period, differentiation means connected between said delay line and said output flip-flop for setting the latter in response to an edge of the delayed digital pulse, and a source of third clock pulses connected to said output flip-flop for resetting same, said first, second and third clock pulses having identical cadences corresponding to the reciprocal of said recurrence period.

3. A counting register as defined in claim 1 wherein said logic gates of each section include an OR gate provided with said single output connection and a plurality of AND gates connected in parallel to the input side of said OR gate.

4. A counting register as defined in claim 3 wherein said feedback means includes bistable means in each stage for delivering a direct output pulse U and a complementary output pulse U respectively representing the true value and the inverted value of a corresponding bit, said second set of leads including a respective conductor pair for each stage, the conductors of said pair being connnected to carry the pulses U, and U, respectively, k being an integer identifying the respective stage.

5. A counting register as defined in claim 4 wherein the number of register stages is greater than two, said command means including switch means for selectively generating an adding command pulse C and its complement C, on a first pair of leads of said first set, a subtracting command pulse C, and its complement C, on a second pair of leads of said first set, an entry command pulse T, and its complement T, on a third pair of leads of said first set, a unit command pulse T, and its complement T, on a fourth pair of leads of said first set, and a plurality of numerical pulses E,, E etc. on respective further leads of said first set, the number of said further leads equaling the number of said memory stages; the logic gates of said first stage comprising a first AND gate connected to receive the complementary first-stage output pulse U, and the command pulses C and T a second AND gate connected to receive the complementary first-stage output pulse U, and the command pulses C, and T a third AND gate connected to receive the first numerical pulse E, and the command pulse T,, a fourth AND gate connected to receive said unit command pulse T,, and a fifth AND gate connected to receive the first-stage output pulse U, and the command pulses C C T, and T,; the logic gates of the second stage comprising a first EXCLUSIVE-OR gate connected to receive the direct output pulses U, and U, of said first and second stages, a second EX- CLUSIVE-OR gate connected to receive the complementary first-stage output pulse U, and the direct second-stage output pulse U a sixth AND gate connected to receive the output of said first EXCLUSIVE-OR gate and the command pulses C T, and T,, a seventh AND gate connected to receive the output of said second EXCLUSIVE-OR gate and the command pulses C,, T, and T an eighth AND gate connected to receive the second numerical pulse E and the command pulses T, and

second-stage output pulse U and the command pulses C C,,

l',. and T5 each further stage comprising a tenth AND gate connected to receive the direct output pulses of all preceding stages, an eleventh AND gate connected to receive the complementary output pulses of all preceding stages, a third EX- CLUSIVE-OR gate connected to receive the output of said tenth AND gate and the direct output pulse of said further stage, a fourth EXCLUSIVE-OR gate connected to receive the output of said eleventh AND gate and the complementary output pulse of said further stage, a twelfth AND gate connected to receive the output of said third EXCLUSIVE-OR gate and the command pulses C,,, T. and T,, a thirteenth AND gate connected to receive the output of said fourth EXCLU- SlVE-OR gate and the command pulses C,, T, and T,, a fourteenth AND gate connected to receive the numerical pulse associated with said further stage and the command pulses T, and T,, and a fifteenth AND gate connected to receive the direct output pulse of said further stage and the commandpulses C,,, C T, and T,; each of said AND gates being further connected to another lead of said first set energizedby said command means in the absence of a cancellation signal.

6. A counting register as defined in claim 4 wherein said command means includes switch means for selectively generating an incremental command pulse and the complement of said incremental command pulse on two leads of said first set, respectively, the logic gates of each stage including a first AND gate connected to one of said two leads for receiving said incremental command pulse and a second AND gate connected to the other of said two leads for receiving said complement thereof, said first AND gate of said first section being further connected to one of the conductors of the corresponding pair for receiving the complementary output pulse U, of said first stage, said second AND gate of any section being further connected to the other conductor of said corresponding pair for receiving the direct output pulse U of the corresponding stage, said first AND gate of each additional section of said logic matrix having input connections to at least one of the paired conductors associated with the corresponding stage and with each lower-order stage.

7. A counting register as defined in claim 6 wherein said incremental command pulse is an adding pulse C, having a complement C said input connections of each additional section of said logic matrix including a logic network connected to supply to said first AND gate thereof the logical function U,, 2,, where Z, is the logical product of the true values of the respective bits of all preceding stages, said first and second AND gates of each additional section being connected to receive directly the command signal C and the complement U respectively.

8. A counting register as defined in claim 6 wherein said incremental command pulse is a subtraction pulse C, having a complement C said input connections of each additional section of said logic matrix including a logic network connected to supply to said first AND gate thereof the logical function U,- Y where Y, is the logical product of the inverted values of the respective bits of all preceding stages, said first and second AND gates of each additional section being connected to receive directly the command signal C, and the complement C,, respectively.

9. A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectively modifying the information so stored, comprising:

a plurality of substantially identical parallel memory stages including each a delay line for the transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said delay line being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said delay line;

a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective delay line thereof;

feedback means connecting the output of each stage with the input thereof through said logic matrix for periodically reinscribing each digital pulse on the same delay line to perpetuate the information stored in said register stages;

and command means connected to said logic matrix for modifying, during a selected recurrence period, the information to be reinscribed;

each of said stages being provided with an input flip-flop and an output flip-flop. a source of first and second clock pulses connected to said input flip-flop for respectively setting and resetting same in the presence of a control pulse in the output of said logic matrix, the input flip-flop being connected to energize said delay line in response to said first and second clock pulses for generating therein a digital pulse of a duration shorter than said recurrence period, differentiation means connected between said delay line and said output flip-flop for setting the latter in response to an edge of the delayed digital pulse, and a source of third clock pulses connected to said output flipflop for resetting same, said first, second and third clock pulses having identical cadences corresponding to the reciprocal of said recurrence period.

10. A counting register as defined in claim 9 wherein said delay line is a magnetostrictive wire provided at one end with a writing coil connected to said input flip-flop and at the other end with a reading coil connected to said output flip-flop.

11. A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectively modifying the information so stored, comprising:

a plurality of substantially identical parallel memory stages including each a magnetorestrictive wire provided at one end with a writing coil and at the other end with a reading coil for the delayed transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the

- delay time of said wire between said coils being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said wire;

a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective wire thereof;

feedback means connecting the reading coil of each stage with the writing coil thereof through said logic matrix for periodicaiyieinscribing each digital pulse on thesame wire to perpetuate the information stored in said register stages;

and command means connected to said logic matrix for modifying, during a selected recurrence period, the information to be reinscribed;

said logic matrix comprising a first section for the lowestorder memory stage and an additional section for each higher-order memory stage, a first set of leads common to all said sections and selectively energizable by said command means, a second set of leads common to all said sections and selectively energizable by said feedback means, and a plurality of said logic gates in each section having input connections to respective combinations of leads from said first and second sets and having a single output connection to the input of the corresponding memory stage. 

1. A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectively modifying the information so stored, comprising: a plurality of substantially identical parallel memory stages including each a delay line for the transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said delay line being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said delay line; a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective delay line thereof; feedback means connecting the output of each stage with the input thereof through said logic matrix for periodically reinscribing each digital pulse on the same delay line to perpetuate the information stored in said register stages; and command means connected to said logic matrix for modifying, during a selected recurrence period, the information to be reinscribed; said logic matrix comprising a first section for the lowestorder memory stage and an additional section for each higherorder memory stage, a first set of leads common to all said sections and selectively energizable by said command means, a second set of leads common to all said sections and selectively energizable by said feedback means, and a plurality of logic gates in each section having input connections to respective combinations of leads from said first and second sets and having a single output connection to the input of the corresponding memory stage.
 2. A counting register as defined in claim 1 wherein each of said stages is provided with an input flip-flop and an output flip-flop, a source of first and second clock pulses connected to said input flip-flop for respectively setting and resetting same in the presence of a control pulse in the output of said logic matrix, the input flip-flop being connected to energize said delay line in response to said first and second clock pulses for generating therein a digital pulse of a duration shorter than said recurrence period, differentiation means connected between said delay line and said output flip-flop for setting the latter in response to an edge of the delayed digital pulse, and a source of third clock pulses connected to said output flip-flop for resetting same, said first, second and third clock pulses having identical cadences corresponding to the reciprocal of said recurrence period.
 3. A counting register as defined in claim 1 wherein said logic gates of each section include an OR gate provided with said single output connection and a plurality of AND gates connected in parallel to the input side of said OR gate.
 4. A counting register as defined in claim 3 wherein said feedback means includes bistable means in each stage for delivering a direct output pulse Uk and a complementary output pulse Uk respectively representing the true value and the inverted value of a corresponding bit, said second set of leads including a respective conductor pair for each stage, the conductors of said pair being connnected to carry the pulses Uk and Uk, respectively, k being an integer identifying the respective stage.
 5. A counting register as defined in claim 4 wherein the number of register stages is greater than two, said command means including switch means for selectively generating an adding command pulse Ca and its complement Ca on a first pair of leads of said first set, a subtracting command pulse Cs and its complement Cs on a second pair of leads of said first set, an entry command pulse Te and its complement Te on a third pair of leads of said first set, a unit command pulse T1 and its complement T1 on a fourth pair of leads of said first set, and a plurality of numerical pulses E1, E2 etc. on respective further leads of said first set, the number of said further leads equaling the number of said memory stages; the logic gates of said first stage comprising a first AND gate connected to receive the complementary first-stage output pulse U1 and the command pulses Ca and Te, a second AND gate connected to receive the complementary first-stage output pulse U1 and the command pulses Cs and Te, a third AND gate connected to receive the first numerical pulse E1 and the command pulse Te, a fourth AND gate connected to receive said unit command pulse T1, and a fifth AND gate connected to receive the first-stage output pulse U1 and the command pulses Ca, Cs, Te and T1; the logic gates of the second stage comprising a first EXCLUSIVE-OR gate connected to receive the direct output pulses U1 and U2 of said first and second stages, a second EXCLUSIVE-OR gate connected to receive the complementary first-stage output pulse U1 and the direct second-stage output pulse U2, a sixth AND gate connected to receive the output of said first EXCLUSIVE-OR gate and the command pulses Ca, Ta and T1, a seventh AND gate connected to receive the output of said second EXCLUSIVE-OR gate and the command pulses Cs, Te and T1, an eighth AND gate connected to receive the second numerical pulse E2 and the command pulses Te and T1, and a ninth AND gate connected to receive the direct second-stage output pulse U2 and the command pulses Ca, Cs, Te and T1; each further stage comprising a tenth AND gate connected to receive the direct output pulses of all preceding stages, an eleventh AND gate connected to receive the complementary output pulses of all preceding stages, a third EXCLUSIVE-OR gate connected to receive the output of said tenth AND gate and the direct output pulse of said further stage, a fourth EXCLUSIVE-OR gate connected to receive the output of said eleventh AND gate and the complementary output pulse of said further stage, a twelfth AND gate connected to receive the output of said third EXCLUSIVE-OR gate and the command pulses Ca, Te and T1, a thirteenth AND gate connected to receive the output of said fourth EXCLUSIVE-OR gate and the command pulses Cs, Te and T1, a fourteenth AND gate connected to receive the numerical pulse associated with said further stage and the command pulses Te and T1, and a fifteenth AND gate connected to receive the direct output pulse of said further stage and the command pulses Ca, Cs, Te and T1; each of said AND gates being further connected to another lead of said first set energized by said command means in the absence of a cancellation signal.
 6. A counting register as defined in claim 4 wherein said command means includes switch means for selectively generating an incremental command pulse and the complement of said incremental command pulse on two leads of said first set, respectively, the logic gates of each stage including a first AND gate connected to one of said two leads for receiving said incremental command pulse and a second AND gate connected to the other of said two leads for receiving said complement thereof, said first AND gate of said first section being further connected to one of the conductors of the corresponding pair for receiving the complementary output pulse U1 of said first stage, said second AND gate of any section being further connected to the other conductor of said corresponding pair for receiving the direct output pulse Uk of the corresponding stage, said first AND gate of each additional section of said logic matrix having input connections to at least one of the paired conductors associated with the corresponding stage and with each lower-order stage.
 7. A counting register as defined in claim 6 wherein said incremental command pulse is an adding pulse Ca having a complement Ca, said input connections of each additional section of said logic matrix including a logic network connected to supply to said first AND gate thereof the logical function Uk + Zk where Zk is the logical product of the true values of the respective bits of all preceding stages, said first and second AND gates of each additional section being connected to receive directly the command signal Ca and the complement Ca, respectively.
 8. A counting register as defined in claim 6 wherein said incremental command pulse is a subtraction pulse Cs having a complement Cs, said input connectiOns of each additional section of said logic matrix including a logic network connected to supply to said first AND gate thereof the logical function Uk + Yk where Yk is the logical product of the inverted values of the respective bits of all preceding stages, said first and second AND gates of each additional section being connected to receive directly the command signal Cs and the complement Cs, respectively.
 9. A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectively modifying the information so stored, comprising: a plurality of substantially identical parallel memory stages including each a delay line for the transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said delay line being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said delay line; a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective delay line thereof; feedback means connecting the output of each stage with the input thereof through said logic matrix for periodically reinscribing each digital pulse on the same delay line to perpetuate the information stored in said register stages; and command means connected to said logic matrix for modifying, during a selected recurrence period, the information to be reinscribed; each of said stages being provided with an input flip-flop and an output flip-flop, a source of first and second clock pulses connected to said input flip-flop for respectively setting and resetting same in the presence of a control pulse in the output of said logic matrix, the input flip-flop being connected to energize said delay line in response to said first and second clock pulses for generating therein a digital pulse of a duration shorter than said recurrence period, differentiation means connected between said delay line and said output flip-flop for setting the latter in response to an edge of the delayed digital pulse, and a source of third clock pulses connected to said output flip-flop for resetting same, said first, second and third clock pulses having identical cadences corresponding to the reciprocal of said recurrence period.
 10. A counting register as defined in claim 9 wherein said delay line is a magnetostrictive wire provided at one end with a writing coil connected to said input flip-flop and at the other end with a reading coil connected to said output flip-flop.
 11. A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectIvely modifying the information so stored, comprising: a plurality of substantially identical parallel memory stages including each a magnetorestrictive wire provided at one end with a writing coil and at the other end with a reading coil for the delayed transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said wire between said coils being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said wire; a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective wire thereof; feedback means connecting the reading coil of each stage with the writing coil thereof through said logic matrix for periodically reinscribing each digital pulse on the same wire to perpetuate the information stored in said register stages; and command means connected to said logic matrix for modifying, during a selected reCurrence period, the information to be reinscribed; said logic matrix comprising a first section for the lowest-order memory stage and an additional section for each higher-order memory stage, a first set of leads common to all said sections and selectively energizable by said command means, a second set of leads common to all said sections and selectively energizable by said feedback means, and a plurality of said logic gates in each section having input connections to respective combinations of leads from said first and second sets and having a single output connection to the input of the corresponding memory stage. 